The present invention relates to a semiconductor device having a micro-fabricated dielectric capacitor, as well as a manufacturing method therefor. More particularly, the invention relates to a semiconductor storage device having a ferroelectric capacitor as well as a manufacturing method therefor.
Nonvolatile ferroelectric memory devices using a ferroelectric typified by Pb(Zr, Ti)O3(PZT) or the like as a capacitor have particularly been receiving attention, in recent years, against the background of their characteristics such as high speed and low power consumption. For high integration of these devices, it is necessary to develop a memory cell structure suitable for microfabrication and to develop a microfabrication technique for a ferroelectric capacitor composed of an upper electrode, a ferroelectric film and a lower electrode. Conventionally, an upper electrode of a ferroelectric capacitor and a diffusion layer (source, drain) of a MOS transistor have been connected to each other by local interconnections. In the stack type memory cell structure, the lower electrode of the ferroelectric capacitor and the diffusion layer are connected to each other by a contact plug, thereby allowing the memory cell area to be reduced. In this case, however, in order to prevent the contact plug formed of polysilicon or the like from reacting with the lower electrode, a barrier metal layer of titanium nitride (TiN) or the like is inserted therebetween. This causes the step gap of the ferroelectric capacitor to increase, which in turn causes occurrence of problem in the later interlayer insulator process or wiring process. Also, in the terraced structure, which is a conventional ferroelectric capacitor structure formed by sequentially etching an upper electrode, a ferroelectric film and a lower electrode, the ferroelectric capacitor, particularly the lower electrode is made of a material of poor processibility such as platinum or iridium, being hard to etch, so that its side wall shows a very gentle slope (taper angle: about 40 degrees). Thus, the terraced structure is a structure which is very hard to micro-fabricate and which is a cause of short-circuit between upper and lower electrodes due to re-deposition of reaction product generated in the etching onto the ferroelectric capacitor.
To solve these problems, Japanese Patent Laid-Open Publication HEI 9-162369 proposes a memory cell structure as shown in FIG. 16. In FIG. 16, there are shown a silicon substrate 1, a gate electrode 2, a diffusion layer (source, drain) 3, a first interlayer insulator 4, a titanium film 201, a TiN plug 202, a second interlayer insulator 8, a lower electrode 10, a ferroelectric film 11, an upper electrode 12, a third interlayer insulator 14, a bit line 15, and a plate line 16.
In the structure disclosed in the above publication, the Ti 201 and the TiN 202 are buried in the contact plug by CVD process so that the step gap of the ferroelectric capacitor can be reduced. Also, the lower electrode 10 is processed before the formation of the ferroelectric film 11 so that short-circuiting between the upper electrode 12 and the lower electrode 10 due to re-deposition during the etching can be prevented.
However, since normal etching technique is used for the processing of the lower electrode, occurrence of tapers at the lower electrode side wall is unavoidable as shown in FIG. 16, making it highly likely that the tapers would make an obstacle in further microfabrication. Also, the contact plug, for which TiN is used, has a thermal resistance of only up to a temperature of about 650xc2x0 C. Therefore, when SrBi2Ta2O9(SBT), which is a ferroelectric material having lower-voltage operation capability and higher reliability than PZT, is used for a ferroelectric capacitor, its formation requires, generally, a temperature of 700xc2x0 C. or higher, which inhibits the use of a TiN plug.
The present invention having been accomplished with a view to solving these and other problems, an object of the invention is to provide a high-integration semiconductor device, as well as a manufacturing method therefor, which allows the lower electrode to be micro-fabricated, as could not be achieved by the prior art, and which enables lower-voltage operation and higher reliability.
In order to achieve the above object, there is provided a semiconductor device comprising:
a diffusion layer formed on a semiconductor substrate;
an interlayer insulator which covers a surface of the semiconductor substrate and whose surface is planarized; and
a dielectric capacitor comprising a lower electrode connected to the diffusion layer via a buried conductive layer which is buried within a contact hole opened in the interlayer insulator and which includes a lower plug member and an upper barrier layer, and a dielectric film formed on the lower electrode, and an upper electrode formed on the dielectric film wherein
the lower electrode has a side-wall sloped configuration that its cross-sectional area monotonously increases from the buried conductive layer side toward the upper dielectric film.
This semiconductor device and manufacturing method therefor can solve the problems of the prior art and are very useful.
More specifically, according to the present invention, since the lower electrode is formed not by dry etching but by CMP process, a micro-fabricated ferroelectric capacitor structure having a lower electrode size of 1.3 xcexcm and a capacitor ferroelectric size of 1.75 xcexcm is formed up. In the structure shown in the prior art, given a taper angle of 40 degrees for processing of lower-electrode iridium, the machining size for the lower electrode (film thickness: 250 nm) including various process margins is 1.4 xcexcm at minimum, which leads to a capacitor ferroelectric size of 1.85 xcexcm. From this fact, the area occupied by the ferroelectric capacitor is about 90% of the prior-art counterpart, showing an effectiveness to further scale-down of microfabrication. Also, according to the present invention, since TaSiN is used for the barrier metal layer, SBT that requires thermal treatment of about 700xc2x0 C. becomes usable, so that a ferroelectric memory device operable at low voltage and having high reliability can be formed.